1. Technical Field
The present invention relates generally to electronic interface bus circuits, and more particularly to a pulsed bus circuit and operating method having dynamic power supply rail selection.
2. Description of the Related Art
Low power electronic systems incorporating large parallel buses are increasingly prevalent, as microprocessor systems are used in notebook computers, personal digital assistants (PDAs) and other electronic appliances designed for portable battery-operated use. Power consumption is also an increasingly important issue in general, as increasing deployment of large-scale computing systems along with an increase in processing power and consequent rise in power consumption raises the cost of operating those systems to businesses and society at-large.
As circuit operating frequencies and die/circuit sizes increase and operating voltages decrease, bus repeaters are necessary in increasing proportion to interconnect internal circuits in high-density electronic devices. The repeaters are necessary to maintain propagation delay and signal skew at tolerable levels as circuit technologies advance. However, inclusion of large numbers of bus repeaters raises quiescent bus power consumption of the device including them significantly, due to an increased number of power supply leakage paths provided through the repeaters, even when the repeaters are inactive. The dynamic bus power consumption is also increased, due to the additional drive elements included on the bus.
One bus repeater solution that has been implemented to reduce the power consumed by interface buses, is a “static pulsed bus.” The static pulsed bus has desirable characteristics in that signal delay and power dissipation due to inter-bus-line coupling capacitance is decreased. Static pulse bus circuits operate by propagating pulses instead of levels, and the pulses are unidirectional for each set of parallel bus segments, reducing the energy used to charge the inter-bus-line coupling capacitance. The presence of a pulse during a period indicates a change in logic state on the particular bus-line and the absence of a pulse indicates no change in logic state. When two parasitically-coupled bus lines transition in the same direction, the effect of the coupling capacitance is zero. When only one bus line transitions, the effect is half of that of the worst-case condition of opposite transitions on the bus lines, which occur in non-pulsed bus designs. Standard buses also have increased current drive requirement in the repeaters in order to overcome the above-described worst-case switching condition, leading to increased leakage through the larger devices.
Therefore, static pulsed bus designs are desirable due to the reduction in both dynamic power consumption due to the reduced effective inter-bit-line capacitance and static leakage current. However, even though static pulsed bus designs lower the power consumption of bus repeater circuits, their power consumption is still significant due to the increasing number of bus repeaters required in emerging electronic devices.
Therefore, it would be desirable to provide a static pulsed bus architecture that further reduces bus power consumption due to leakage and dynamic power consumption.